Datasheet

CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
†
All inputs are protected by CMOS protection network.
11
10
9
6
A
B
C
INH
134 2 5 1 12 15 14
TG
TG
TG
TG
TG
TG
TG
TG
3
COM
OUT/IN
01234567
8 7
16
CHANNEL I/O
†
†
†
†
CD4051B
Logic-Level
Conversion
Binary
to
1-of-8
Decoder
With
Inhibit
V
DD
V
SS
V
EE
†
All inputs are protected by CMOS protection network.
CD4052B
1211 15 14
0123
3210
X CHANNEL I/O
Y CHANNEL I/O
13
3
78
16
6
9
10
A
B
INH
TG
TG
TG
TG
TG
TG
TG
TG
4251
Binary
to
1-of-4
Decoder
With
Inhibit
†
†
†
COM X
OUT/IN
Logic-Level
Conversion
V
DD
V
SS
V
EE
COM Y
OUT/IN