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CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4051
V
DD
I
DD
CD4052
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4052
V
DD
I
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4053
V
DD
I
DD
Figure 12. OFF Channel Leakage Current, Any Channel OFF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4051
V
DD
I
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4052
V
DD
I
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4053
V
DD
I
DD
Figure 13. OFF Channel Leakage Current, All Channels OFF
V
SS
R
L
CD4051
Clock
In
Output
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
V
DD
V
EE
V
SS
V
DD
V
SS
V
EE
C
L
V
DD
C
L
CD4052
Clock
In
Output
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
V
SS
V
EE
V
DD
V
SS
V
SS
V
EE
R
L
V
DD
V
DD
V
EE
V
EE
V
SS
V
SS
V
SS
CD4053
Clock
In
R
L
C
L
Output
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Figure 14. Propagation Delay, Address Input to Signal Output
V
SS
V
EE
t
PHL
and t
PLH
V
SS
V
DD
V
SS
Output
CD4051
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Clock
In
50 pF
V
DD
V
EE
V
DD
R
L
V
SS
V
DD
V
EE
V
SS
t
PHL
and t
PLH
CD4052
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Output
Clock
In
50 pF
R
L
V
EE
V
SS
V
DD
V
DD
V
DD
V
EE
V
SS
V
EE
t
PHL
and t
PLH
Clock
In
CD4053
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
V
DD
Output
R
L
V
SS
V
SS
50 pF
Figure 15. Propagation Delay, Inhibit Input to Signal Output