Datasheet

CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
NOTE: The A, B, C, and INH input logic levels are L = V
SS
and H = V
DD
. The analog signal (through the TG) may swing from V
EE
to V
DD
.
7
8
(B)
(C)
(D)
(A)
1616 1616
7
8
7
8
7
8
5 V 5 V
V
SS
= 0 V
V
SS
= 0 V
V
SS
= 0 V
V
SS
= 0 V
V
EE
= –5 V
V
EE
= –10 V
V
EE
= –7.5 V
V
EE
= 0 V
V
DD
= 15 V V
DD
= 7.5 V V
DD
= 5 V V
DD
= 5 V
7.5 V
Figure 9. Typical Bias-Voltage Test Circuits
Figure 10. Channel Turned ON Waveforms
(R
L
= 1 kΩ)
t
f
= 20 ns
10%
10%
90%
50%
10%
50%
90%
10%
50%
90%
t
r
= 20 ns
Turn-Off Time
Turn-On Time
Figure 11. Channel Turned OFF Waveforms
(R
L
= 1 kΩ)
t
f
= 20 ns
10%
90%
50%
10%
50%
90%
10%
90%
t
r
= 20 ns
Turn-Off Time
Turn-On Time
t
PHZ