Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - multiplexers, demultiplexers TSSOP 16

CD4051B-Q1, CD4052B-Q1, CD4053B-Q1

CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS

WITH LOGIC−LEVEL CONVERSION

SCHS354A − AUGUST 2004 − REVISED JANUARY 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Features

D Qualified for Automotive Applications

D Wide Range of Digital and Analog Signal

Levels

− Digital: 3 V to 20 V

− Analog: 3 20 V

P-P

D Low ON Resistance, 125 Ω (Typ) Over

15 V

P-P

Signal Input Range

for V

− V

= 18 V

D High OFF Resistance, Channel Leakage of

+100 pA (Typ) at V

− V

= 18 V

D Logic-Level Conversion for Digital

Addressing Signals of 3 V to 20 V

− V

= 3 V to 20 V) to Switch Analog

Signals to 20 V

P-P

− V

= 20 V)

D Matched Switching Characteristics,

= 5 Ω (Typ) for V

− V

= 15 V

D Very Low Quiescent Power Dissipation

Under All Digital-Control Input and Supply

Conditions, 0.2 µW (Typ)

at V

− V

= V

− V

= 10 V

D Binary Address Decoding on Chip

D 5-V, 10-V, and 15-V Parametric Ratings

D 100% Tested for Quiescent Current at 20 V

D Maximum Input Current of 1µA at 18 V Over

Full Package Temperature Range, 100 nA at

18 V and 25°C

D Break-Before-Make Switching Eliminates

Channel Overlap

Applications

D Analog and Digital Multiplexing and

Demultiplexing

D Analog-to-Digital (A/D) and

Digital-to-Analog (D/A) Conversion

D Signal Gating

description/ordering information

The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches that have

low ON impedance and very low OFF leakage current. Control of analog signals up to 20 V

P-P

can be achieved

by digital signal amplitudes of 4.5 V to 20 V (If V

− V

= 3 V, a V

− V

of up to 13 V can be controlled;

for V

− V

level differences above 13 V, a V

− V

of at least 4.5 V is required). For example, if

= 4.5 V, V

= 0 V, and V

= −13.5 V, analog signals from −13.5 V to 4.5 V can be controlled by digital

inputs of 0 V to 5 V. These multiplexer circuits dissipate extremely low quiescent power over the full V

− V

and V

− V

supply-voltage ranges, independent of the logic state of the control signals. When a logic high

(H) is present at the inhibit (INH) input, all channels are off.

ORDERING INFORMATION

†

PACKAGE

‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − M Reel of 2500 CD4051BQM96Q1 CD4051Q

TSSOP − PW Reel of 2000 CD4051BQPWRQ1 CM051BQ

C to 125

SOIC − M Reel of 2500 CD4052BQM96Q1

CD4052Q

−40°C to 125°C

TSSOP − PW Reel of 2000 CD4052BQPWRQ1

CD4052Q

SOIC − M Reel of 2500 CD4053BQM96Q1 CD4053Q

TSSOP − PW Reel of 2000 CD4053BQPWRQ1

CD4053Q

†

For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or see the TI web site at http://www.ti.com.

‡

Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

Product Preview

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (24 pages)

PAGE 1
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 D Very Low Quiescent Power Dissipation Features D Qualified for Automotive Applications D Wide Range of Digital and Analog Signal D D D D Levels − Digital: 3 V to 20 V − Analog: 3 20 VP-P Low ON Resistance, 125 Ω (Typ) Over 15 VP-P Signal Input Range for VDD − VEE = 18 V High OFF Resistance, Channel Leakage of +100 pA (Typ) at VDD − VEE = 18 V Logic-Level
PAGE 2
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 description/ordering information (continued) The CD4051B is a single eight-channel multiplexer that has three binary control inputs (A, B, and C) and an inhibit input. The three binary signals select one of eight channels to be turned on and connect one of the eight inputs to the output.
PAGE 3
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 Function Tables CD4051 INPUTS B ON CHANNEL INH C L L L L 0 L L L H 1 L L H L 2 L L H H 3 L H L L 4 L H L H 5 L H H L 6 L H H H 7 H X X X None A X = don’t care CD4052 INPUTS INH B A ON CHANNEL L L L 0x, 0y L L H 1x, 2y L H L 2x, 2y L H H 3x, 3y H X X None X = don’t care CD4053 INPUTS INH
PAGE 4
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 logic diagram (positive logic) CD4051B CHANNEL I/O 16 VDD 7 6 5 4 3 2 1 0 4 2 5 1 12 15 14 13 TG TG A† 11 TG † B Binary to 1-of-8 Decoder With Inhibit 10 Logic-Level Conversion C† 9 TG 3 COM OUT/IN TG TG TG † INH 6 TG 8 † 7 VSS VEE All inputs are protected by CMOS protection network.
PAGE 5
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 logic diagrams (positive logic) (continued) CD4053B IN/OUT 16 VDD A† 11 cy cx by bx ay ax 3 5 1 2 13 12 Binary to 1-of-2 Decoders With Inhibit Logic-Level Conversion TG COM OUT/IN ac or ay 14 TG TG B† 10 COM OUT/IN bc or by 15 TG C† TG 9 COM OUT/IN xc or xy 4 TG INH† 6 VDD 8 VSS † 7 VEE All inputs are protected by standard CMOS
PAGE 6
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 recommended operating conditions VDD Supply voltage TA Operating free-air temperature MIN MAX 5 20 UNIT V −40 125 °C electrical characteristics, VSUPPLY = ±5 V, AV = 1 V, RL = 100 Ω, unless otherwise noted (see Note 2) PARAMETER IDD VDD (V) TEST CONDITIONS Quiescent device current LIMITS AT INDICATED TEMPERATURES UNIT 25°C −40°C 40°C 125°C
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CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 electrical characteristics, VSUPPLY = ±5 V, AV = 1 V, RL = 100 Ω, unless otherwise noted (see Note 2) (continued) PARAMETER TEST CONDITIONS VEE (V) VDD (V) LIMITS AT INDICATED TEMPERATURES UNIT 25°C −40°C 40°C 125°C MIN TYP MAX Control (Address or Inhibit), VC VIL VIH IIN tpd1 tpd2 tpd3 CIN Input p low voltage g Input p high g voltage g Inpu
PAGE 8
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 electrical specifications PARAMETER VIS (V) TEST CONDITIONS VDD (V) LIMITS AT INDICATED TEMPERATURES MIN −3-dB cutoff frequency frequency, channel ON (sine-wave input) THD Total harmonic distortion RL = 1 kΩ,, VOS at COM OUT/IN, See Note 2, 2 VOS at COM OUT/IN 5 10 30 CD4052 5 10 25 CD4051 5 10 20 kΩ RL = 10 kΩ, See Note 2 2 5 3 10 0.
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CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 TYPICAL CHARACTERISTICS 600 Supply Voltage (VDD − VEE) = 5 V 500 TA = 125°C CHANNEL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE 400 300 25°C 200 −55°C 100 0 −4 −3 −2 −1 0 1 2 3 4 ron − Channel ON−State Resistance − W ron − Channel ON−State Resistance − W CHANNEL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE 300 Supply Voltage (VDD − VEE) = 10 V
PAGE 10
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 TYPICAL CHARACTERISTICS DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4051B) PD − Power Dissipation Per Package − mW ON CHARACTERISTICS FOR 1-OF-8 CHANNELS (CD4051B) Vos − Output Signal Voltage − V 6 VDD = 5 V RL = 100 kW, RL = 10 kW VSS = 0 V 4 1 kW 500 W VEE = −5 V 100 W TA = 255C 2 0 −2 −4 −6 −6 −4 −2 0 2 4 6 10 5 TA = 255C Test C
PAGE 11
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 PARAMETER MEASUREMENT INFORMATION VDD = 15 V VDD = 7.5 V VDD = 5 V 5V 7.5 V 16 VDD = 5 V 5V 16 16 16 VSS = 0 V VSS = 0 V VSS = 0 V VEE = 0 V 7 8 VSS = 0 V VEE = –7.5 V 7 8 VEE = –10 V VEE = –5 V 7 8 (D) (C) (B) (A) 7 8 NOTE: The A, B, C, and INH input logic levels are L = VSS and H = VDD.
PAGE 12
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 PARAMETER MEASUREMENT INFORMATION 1 2 3 4 5 6 7 16 15 14 13 12 11 10 8 9 VDD VDD VDD 1 2 3 4 5 6 7 8 IDD CD4051 16 15 14 13 12 11 10 CD40529 1 2 3 4 5 6 7 8 IDD 16 15 14 13 12 11 10 9 IDD CD4053 CD4052 Figure 12.
PAGE 13
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 PARAMETER MEASUREMENT INFORMATION VDD VDD VDD µA VIH 1K 1K VIH VIL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CD4051B VIH VIL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1K 1K µA VIH 1K VIL VIH 16 15 14 13 12 11 10 9 1K mA VIH VIL CD4053B CD4052B VIL 1 2 3 4 5 6 7 8 VIL Measure <2 mA on All OFF Channels (e.g.
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CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 PARAMETER MEASUREMENT INFORMATION VDD 1 2 3 4 5 6 7 8 VSS VDD 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VDD Ι VSS CD4051 CD4053 VSS NOTE: Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS. 16 15 14 13 12 11 10 9 VDD Ι VSS CD4051 CD4053 NOTE: Measure inputs sequentially to both VDD and VSS.
PAGE 15
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC−LEVEL CONVERSION SCHS354A − AUGUST 2004 − REVISED JANUARY 2008 APPLICATION INFORMATION In applications where separate power sources drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4051B, CD4052B, or CD4053B.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD4051BQPWRG4Q1 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD4051BQPWRQ1 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD4051BQPWRG4Q1 TSSOP PW 16 2000 367.0 367.0 35.0 CD4051BQPWRQ1 TSSOP PW 16 2000 367.0 367.0 35.
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