Datasheet

14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
by
bx
cy
OUT/IN CX OR CY
IN/OUT CX
INH
V
V
V
OUT/IN ax OR ay
SS
EE
DD
ay
ax
A
B
C
OUT/IN bx OR by
IN/OUT
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
0
2
COMMON “Y” OUT/IN
3
1
INH
V
V
V
1
SS
EE
DD
COMMON “X” OUT/IN
0
3
A
B
2
Y CHANNELS
IN/OUT
Y CHANNELS
IN/OUT
X CHANNELS
IN/OUT
X CHANNELS
IN/OUT
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
4
6
COM OUT/IN
7
5
INH
V
V
V
1
SS
EE
DD
0
3
A
B
C
2
CHANNELS IN/OUT
CHANNELS
IN/OUT
CHANNELS
IN/OUT
3
CD4051B , CD4052B , CD4053B
www.ti.com SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017
Product Folder Links: CD4051B CD4052B CD4053B
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5 Pin Configuration and Functions
CD4051B E, M, NS, and PW Package
16-Pin PDIP, CDIP, SOIC, SOP, and TSSOP
(Top View)
CD4052B E, M, NS, and PW Package
16-Pin PDIP, CDIP, SOP, and TSSOP
(Top View)
CD4053B E, M, NS, and PW Package
16-Pin PDIP, CDIP, SOP, and TSSOP
(Top View)
Pin Functions CD4051B
PIN
I/O DESCRIPTION
NO. NAME
1 CH 4 IN/OUT I/O Channel 4 in/out
2 CH 6 IN/OUT I/O Channel 6 in/out
3 COM OUT/IN I/O Common out/in
4 CH 7 IN/OUT I/O Channel 7 in/out
5 CH 5 IN/OUT I/O Channel 5 in/out
6 INH I Disables all channels. See Table 1.
7 V
EE
— Negative power input
8 V
SS
— Ground
9 C I Channel select C. See Table 1.
10 B I Channel select B. See Table 1.
11 A I Channel select A. See Table 1.
12 CH 3 IN/OUT I/O Channel 3 in/out
13 CH 0 IN/OUT I/O Channel 0 in/out
14 CH 1 IN/OUT I/O Channel 1 in/out
15 CH 2 IN/OUT I/O Channel 2 in/out
16 V
DD
— Positive power input