Datasheet
MOTOROLA CMOS LOGIC DATAMC14040B
152
SWITCHING CHARACTERISTICS (C
L
= 50 pF, T
A
= 25 C)
Characteristic Symbol
V
DD
Vdc
Min Typ # Max Unit
Output Rise and Fall Time
T
TLH
, T
THL
= (1.5 ns/pF) C
L
+ 25 ns
T
TLH
, T
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
T
TLH
, T
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q1
t
PHL
, t
PLH
= (1.7 ns/pF) C
L
+ 315 ns
t
PHL
, t
PLH
= (0.66 ns/pF) C
L
+ 137 ns
t
PHL
, t
PLH
= (0.5 ns/pF) C
L
+ 95 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
260
115
80
520
230
160
ns
Clock to Q12
t
PHL
, t
PLH
= (1.7 ns/pF) C
L
+ 2415 ns
t
PHL
, t
PLH
= (0.66 ns/pF) C
L
+ 867 ns
t
PHL
, t
PLH
= (0.5 ns/pF) C
L
+ 475 ns
5.0
10
15
—
—
—
1625
720
500
3250
1440
1000
ns
Propagation Delay Time
Reset to Q
n
t
PHL
= (1.7 ns/pF) C
L
+ 485 ns
t
PHL
= (0.86 ns/pF) C
L
+ 182 ns
t
PHL
= (0.5 ns/pF) C
L
+ 145 ns
t
PHL
5.0
10
15
—
—
—
370
155
115
740
310
230
ns
Clock Pulse Width t
WH
5.0
10
15
385
150
115
140
55
38
—
—
—
ns
Clock Pulse Frequency f
cl
5.0
10
15
—
—
—
2.1
7.0
10.0
1.5
3.5
4.5
MHz
Clock Rise and Fall Time t
TLH
, t
THL
5.0
10
15
No Limit
ns
Reset Pulse Width t
WH
5.0
10
15
960
360
270
320
120
80
—
—
—
ns
Reset Removal Time t
rem
5.0
10
15
130
50
30
65
25
15
—
—
—
ns
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Power Dissipation Test Circuit
and Waveform
Figure 2. Switching Time Test Circuit
and Waveforms
PULSE
GENERATOR
PULSE
GENERATOR
500
µ
F
0.01
µ
F
CERAMIC
V
DD
V
SS
C
L
C
L
C
L
I
D
Q1
Q2
Q
n
C
R
20 ns 20 ns
V
DD
V
SS
90%
50%
10%
CLOCK
50% DUTY CYCLE
V
DD
V
SS
C
L
C
L
C
L
Q1
Q2
Q
n
C
R
20 ns 20 ns
CLOCK
90%
50%
10%
t
WH
t
PHL
t
PLH
Q
90%
50%
10%
t
TLH
t
THL