Datasheet

CC3100
www.ti.com SWAS031D –JUNE 2013–REVISED FEBRUARY 2015
5.4.2 Preregulated 1.85 V
The preregulated 1.85-V mode of operation applies an external regulated 1.85 V directly at the pins 10,
25, 33, 36, 37, 39, 44, 48, and 54 of the device. The VBAT and the VIO are also connected to the 1.85-V
supply. This mode provides the lowest BOM count version in which inductors used for PA DC-DC and
ANA1 DC-DC (2.2 and 1 µH) and a capacitor (22 µF) can be avoided. For electrical connections, see
Section 6.1.2, Typical Application – CC3100 Preregulated 1.85-V Mode.
In the preregulated 1.85-V mode, the regulator providing the 1.85 V must have the following
characteristics:
• Load current capacity ≥900 mA.
• Line and load regulation with <2% ripple with 500 mA step current and settling time of <4 µs with the
load step.
• The regulator must be placed very close to the CC3100 device so that the IR drop to the device is very
low.
5.5 Low-Power Operating Modes
This section describes the low-power modes supported by the device to optimize battery life.
5.5.1 Low-Power Deep Sleep
The low-power deep-sleep (LPDS) mode is an energy-efficient and transparent sleep mode that is entered
automatically during periods of inactivity based on internal power optimization algorithms. The device can
wake up in less than 3 ms from the internal timer or from any incoming host command. Typical battery
drain in this mode is 115 µA. During LPDS mode, the device retains the software state and certain
configuration information. The operation is transparent to the external host; thus, no additional handshake
is required to enter or exit this sleep mode.
5.5.2 Hibernate
The hibernate mode is the lowest power mode in which all of the digital logic is power-gated. Only a small
section of the logic powered directly by the main input supply is retained. The real-time clock (RTC) is kept
running and the device wakes up once the nHIB line is asserted by the host driver. The wake-up time is
longer than LPDS mode at about 50 ms.
NOTE
Wake-up time can be extended to 75 ms if a patch is loaded from the serial flash.
5.6 Memory
5.6.1 External Memory Requirements
The CC3100 device maintains a proprietary file system on the SFLASH. The CC3100 file system stores
the service pack file, system files, configuration files, certificate files, web page files, and user files. By
using a format command through the API, users can provide the total size allocated for the file system.
The starting address of the file system cannot be set and is always located at the beginning of the
SFLASH. The applications microcontroller must access the SFLASH memory area allocated to the file
system directly through the CC3100 file system. The applications microcontroller must not access the
SFLASH memory area directly.
The file system manages the allocation of SFLASH blocks for stored files according to download order,
which means that the location of a specific file is not fixed in all systems. Files are stored on SFLASH
using human-readable file names rather than file IDs. The file system API works using plain text, and file
encryption and decryption is invisible to the user. Encrypted files can be accessed only through the file
system.
Copyright © 2013–2015, Texas Instruments Incorporated Detailed Description 29
Submit Documentation Feedback
Product Folder Links: CC3100