User manual

Cortex-M3 Processor Registers

www.ti.com

2.7.2.5 SLEEPCNT Register (Offset = 10h) [reset = X]

SLEEPCNT is shown in Figure 2-45 and described in Table 2-69.

Sleep Count This register is used to count the total number of cycles during which the processor is

sleeping.

Figure 2-45. SLEEPCNT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED SLEEPCNT

R/W-X R/W-0h

Table 2-69. SLEEPCNT Register Field Descriptions

Bit Field Type Reset Description

31-8 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

7-0 SLEEPCNT R/W 0h

Sleep counter. Counts the number of cycles during which the

processor is sleeping. An event is emitted on counter overflow (every

256 cycles). This counter initializes to 0 when it is enabled using

CTRL.SLEEPEVTENA. Note that the sleep counter is clocked using

CPU's free-running clock. In some power modes the free-running

clock to CPU is gated to minimize power consumption. This means

that the sleep counter will be invalid in these power modes.

SWCU117A–February 2015–Revised March 2015

Submit Documentation Feedback