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Cortex-M3 Processor Registers

2.7.2.4 EXCCNT Register (Offset = Ch) [reset = X]

EXCCNT is shown in Figure 2-44 and described in Table 2-68.

Exception Overhead Count This register is used to count the total cycles spent in interrupt processing.

Figure 2-44. EXCCNT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EXCCNT

R/W-X R/W-0h

Table 2-68. EXCCNT Register Field Descriptions

Bit Field Type Reset Description

31-8 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

7-0 EXCCNT R/W 0h

Current interrupt overhead counter value. Counts the total cycles

spent in interrupt processing (for example entry stacking, return

unstacking, pre-emption). An event is emitted on counter overflow

(every 256 cycles). This counter initializes to 0 when it is enabled

using CTRL.EXCEVTENA.

SWCU117A–February 2015–Revised March 2015

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