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Cortex-M3 Processor Registers

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2.7.2.3 CPICNT Register (Offset = 8h) [reset = X]

CPICNT is shown in Figure 2-43 and described in Table 2-67.

CPI Count This register is used to count the total number of instruction cycles beyond the first cycle.

Figure 2-43. CPICNT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CPICNT

R/W-X R/W-0h

Table 2-67. CPICNT Register Field Descriptions

Bit Field Type Reset Description

31-8 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

7-0 CPICNT R/W 0h

Current CPI counter value. Increments on the additional cycles (the

first cycle is not counted) required to execute all instructions except

those recorded by LSUCNT. This counter also increments on all

instruction fetch stalls. If CTRL.CPIEVTENA is set, an event is

emitted when the counter overflows. This counter initializes to 0

when it is enabled using CTRL.CPIEVTENA.

SWCU117A–February 2015–Revised March 2015

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