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Cortex-M3 Processor Registers

2.7.2.2 CYCCNT Register (Offset = 4h) [reset = X]

CYCCNT is shown in Figure 2-42 and described in Table 2-66.

Current PC Sampler Cycle Count This register is used to count the number of core cycles. This counter

can measure elapsed execution time. This is a free-running counter (this counter will not advance in

power modes where free-running clock to CPU stops). The counter has three functions: 1: When

CTRL.PCSAMPLEENA = 1, the PC is sampled and emitted when the selected tapped bit changes value

(0 to 1 or 1 to 0) and any post-scalar value counts to 0. 2: When CTRL.CYCEVTENA = 1 , (and

CTRL.PCSAMPLEENA = 0), an event is emitted when the selected tapped bit changes value (0 to 1 or 1

to 0) and any post-scalar value counts to 0. 3: Applications and debuggers can use the counter to

measure elapsed execution time. By subtracting a start and an end time, an application can measure time

between in-core clocks (other than when Halted in debug). This is valid to 2^32 core clock cycles (for

example, almost 89.5 seconds at 48MHz).

Figure 2-42. CYCCNT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CYCCNT

R/W-X

Table 2-66. CYCCNT Register Field Descriptions

Bit Field Type Reset Description

31-0 CYCCNT R/W X

Current PC Sampler Cycle Counter count value. When enabled, this

counter counts the number of core cycles, except when the core is

halted. The cycle counter is a free running counter, counting

upwards (this counter will not advance in power modes where free-

running clock to CPU stops). It wraps around to 0 on overflow. The

debugger must initialize this to 0 when first enabling.

SWCU117A–February 2015–Revised March 2015

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