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www.ti.com Cortex-M3 Processor Registers
2.7.2.1 CTRL Register (Offset = 0h) [reset = X]
CTRL is shown in Figure 2-41 and described in Table 2-65.
Control Use the DWT Control Register to enable the DWT unit.
Figure 2-41. CTRL Register
31 30 29 28 27 26 25 24
RESERVED NOCYCCNT NOPRFCNT
R/W-10h R/W-X R/W-X
23 22 21 20 19 18 17 16
RESERVED CYCEVTENA FOLDEVTENA LSUEVTENA SLEEPEVTEN EXCEVTENA CPIEVTENA EXCTRCENA
A
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
15 14 13 12 11 10 9 8
RESERVED PCSAMPLEEN SYNCTAP CYCTAP POSTCNT
A
R/W-X R/W-X R/W-X R/W-X R/W-X
7 6 5 4 3 2 1 0
POSTCNT POSTPRESET CYCCNTENA
R/W-X R/W-X R/W-X
Table 2-65. CTRL Register Field Descriptions
Bit Field Type Reset Description
31-26 RESERVED R/W 10h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
25 NOCYCCNT R/W X
When set, CYCCNT is not supported.
24 NOPRFCNT R/W X
When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and
CPICNT are not supported.
23 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
22 CYCEVTENA R/W X
Enables Cycle count event. Emits an event when the POSTCNT
counter triggers it. See CYCTAP and POSTPRESET for details. This
event is only emitted if PCSAMPLEENA is disabled.
PCSAMPLEENA overrides the setting of this bit. 0: Cycle count
events disabled 1: Cycle count events enabled
21 FOLDEVTENA R/W X
Enables Folded instruction count event. Emits an event when
FOLDCNT overflows (every 256 cycles of folded instructions). A
folded instruction is one that does not incur even one cycle to
execute. For example, an IT instruction is folded away and so does
not use up one cycle. 0: Folded instruction count events disabled. 1:
Folded instruction count events enabled.
20 LSUEVTENA R/W X
Enables LSU count event. Emits an event when LSUCNT overflows
(every 256 cycles of LSU operation). LSU counts include all LSU
costs after the initial cycle for the instruction. 0: LSU count events
disabled. 1: LSU count events enabled.
19 SLEEPEVTENA R/W X
Enables Sleep count event. Emits an event when SLEEPCNT
overflows (every 256 cycles that the processor is sleeping). 0: Sleep
count events disabled. 1: Sleep count events enabled.
18 EXCEVTENA R/W X
Enables Interrupt overhead event. Emits an event when EXCCNT
overflows (every 256 cycles of interrupt overhead). 0x0: Interrupt
overhead event disabled. 0x1: Interrupt overhead event enabled.
17 CPIEVTENA R/W X
Enables CPI count event. Emits an event when CPICNT overflows
(every 256 cycles of multi-cycle instructions). 0: CPI counter events
disabled. 1: CPI counter events enabled.
16 EXCTRCENA R/W X
Enables Interrupt event tracing. 0: Interrupt event trace disabled. 1:
Interrupt event trace enabled.
93
SWCU117A–February 2015–Revised March 2015
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