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Cortex-M3 Processor Registers

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2.7.2 CPU_DWT Registers

Table 2-64 lists the memory-mapped registers for the CPU_DWT. All register offset addresses not listed in

Table 2-64 should be considered as reserved locations and the register contents should not be modified.

Table 2-64. CPU_DWT Registers

Offset Acronym Register Name Section

0h CTRL Control Section 2.7.2.1

4h CYCCNT Current PC Sampler Cycle Count Section 2.7.2.2

8h CPICNT CPI Count Section 2.7.2.3

Ch EXCCNT Exception Overhead Count Section 2.7.2.4

10h SLEEPCNT Sleep Count Section 2.7.2.5

14h LSUCNT LSU Count Section 2.7.2.6

18h FOLDCNT Fold Count Section 2.7.2.7

1Ch PCSR Program Counter Sample Section 2.7.2.8

20h COMP0 Comparator 0 Section 2.7.2.9

24h MASK0 Mask 0 Section 2.7.2.10

28h FUNCTION0 Function 0 Section 2.7.2.11

30h COMP1 Comparator 1 Section 2.7.2.12

34h MASK1 Mask 1 Section 2.7.2.13

38h FUNCTION1 Function 1 Section 2.7.2.14

40h COMP2 Comparator 2 Section 2.7.2.15

44h MASK2 Mask 2 Section 2.7.2.16

48h FUNCTION2 Function 2 Section 2.7.2.17

50h COMP3 Comparator 3 Section 2.7.2.18

54h MASK3 Mask 3 Section 2.7.2.19

58h FUNCTION3 Function 3 Section 2.7.2.20

SWCU117A–February 2015–Revised March 2015

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