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Cortex-M3 Processor Registers

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Table 2-61. TCR Register Field Descriptions (continued)

Bit Field Type Reset Description

1 TSENA R/W X

Enables differential timestamps. Differential timestamps are emitted

when a packet is written to the FIFO with a non-zero timestamp

counter, and when the timestamp counter overflows. Timestamps

are emitted during idle times after a fixed number of two million

cycles. This provides a time reference for packets and inter-packet

gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity

on the internal trace bus only. In this case there is no regular

timestamp output when the ITM is idle.

0 ITMENA R/W X

Enables ITM. This is the master enable, and must be set before ITM

Stimulus and Trace Enable registers can be written.

SWCU117A–February 2015–Revised March 2015

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