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10.2.1.39 IRQSTAT Register (Offset = 790h) [reset = X]
IRQSTAT is shown in Figure 10-41 and described in Table 10-49.
Interrupt Status
Figure 10-41. IRQSTAT Register
31 30 29 28 27 26 25 24
DMA_BUS_ER KEY_ST_WR_ KEY_ST_RD_E RESERVED
R ERR RR
R-X R-X R-X R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED DMA_IN_DON RESULT_AVAI
E L
R-X R-X R-X
Table 10-49. IRQSTAT Register Field Descriptions
Bit Field Type Reset Description
31 DMA_BUS_ERR R X
This bit is set when a DMA bus error is detected during a DMA
operation. The value of this register is held until it is cleared via
IRQCLR.DMA_BUS_ERR Note: This error is asserted if an error is
detected on the AHB master interface during a DMA operation. Note:
This is not an interrupt source.
30 KEY_ST_WR_ERR R X
This bit is set when a write error is detected during the DMA write
operation to the key store memory. The value of this register is held
until it is cleared via IRQCLR.KEY_ST_WR_ERR Note: This error is
asserted if a DMA operation does not cover a full key area or more
areas are written than expected. Note: This is not an interrupt
source.
29 KEY_ST_RD_ERR R X
This bit will be set when a read error is detected during the read of a
key from the key store, while copying it to the AES engine. The value
of this register is held until it is cleared via
IRQCLR.KEY_ST_RD_ERR. Note: This error is asserted if a key
location is selected in the key store that is not available. Note: This is
not an interrupt source.
28-2 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
1 DMA_IN_DONE R X
This bit returns the status of DMA data in done interrupt.
0 RESULT_AVAIL R X
This bit is set high when the Crypto peripheral has a result available.
865
SWCU117A–February 2015–Revised March 2015
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