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Cryptography Registers

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10.2.1.38 IRQSET Register (Offset = 78Ch) [reset = X]

IRQSET is shown in Figure 10-40 and described in Table 10-48.

Interrupt Set

Figure 10-40. IRQSET Register

31 30 29 28 27 26 25 24

RESERVED

W-X

23 22 21 20 19 18 17 16

RESERVED

W-X

15 14 13 12 11 10 9 8

RESERVED

W-X

7 6 5 4 3 2 1 0

RESERVED DMA_IN_DON RESULT_AVAI

E L

W-X W-X W-X

Table 10-48. IRQSET Register Field Descriptions

Bit Field Type Reset Description

31-2 RESERVED W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

1 DMA_IN_DONE W X

If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set. Writing 0

has no effect.

0 RESULT_AVAIL W X

If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set. Writing 0

has no effect.

864

SWCU117A–February 2015–Revised March 2015

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