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Cryptography Registers

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10.2.1.36 IRQEN Register (Offset = 784h) [reset = X]

IRQEN is shown in Figure 10-38 and described in Table 10-46.

Interrupt Enable

Figure 10-38. IRQEN Register

31 30 29 28 27 26 25 24

RESERVED

R/W-X

23 22 21 20 19 18 17 16

RESERVED

R/W-X

15 14 13 12 11 10 9 8

RESERVED

R/W-X

7 6 5 4 3 2 1 0

RESERVED DMA_IN_DON RESULT_AVAI

E L

R/W-X R/W-X R/W-X

Table 10-46. IRQEN Register Field Descriptions

Bit Field Type Reset Description

31-2 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

1 DMA_IN_DONE R/W X

This bit enables IRQSTAT.DMA_IN_DONE as source for IRQ.

0 RESULT_AVAIL R/W X

This bit enables IRQSTAT.RESULT_AVAIL as source for IRQ.

862

SWCU117A–February 2015–Revised March 2015

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