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Cryptography Registers

10.2.1.35 IRQTYPE Register (Offset = 780h) [reset = X]

IRQTYPE is shown in Figure 10-37 and described in Table 10-45.

Interrupt Configuration

Figure 10-37. IRQTYPE Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

R/W-X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED IEN

R/W-X R/W-X

Table 10-45. IRQTYPE Register Field Descriptions

Bit Field Type Reset Description

31-1 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

0 IEN R/W X

Interrupt enable. This bit must be set to 1 to enable interrupts from

the Crypto peripheral. 0 : All interrupts are disabled enabled. 1 : All

interrupts are enabled.

861

SWCU117A–February 2015–Revised March 2015

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