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Cryptography Registers

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10.2.1.34 SWRESET Register (Offset = 740h) [reset = X]

SWRESET is shown in Figure 10-36 and described in Table 10-44.

Software Reset

Figure 10-36. SWRESET Register

31 30 29 28 27 26 25 24

RESERVED

R/W-X

23 22 21 20 19 18 17 16

RESERVED

R/W-X

15 14 13 12 11 10 9 8

RESERVED

R/W-X

7 6 5 4 3 2 1 0

RESERVED RESET

R/W-X R/W1C-X

Table 10-44. SWRESET Register Field Descriptions

Bit Field Type Reset Description

31-1 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

0 RESET R/W1C X

If this bit is set to 1, the following modules are reset: - Master control

internal state is reset. That includes interrupt, error status register

and result available interrupt generation FSM. - Key store module

state is reset. That includes clearing the Written Area flags; therefore

the keys must be reloaded to the key store module. Writing 0 has no

effect. The bit is self cleared after executing the reset.

860

SWCU117A–February 2015–Revised March 2015

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