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Cortex-M3 Processor Registers

Table 2-59. TER Register Field Descriptions (continued)

Bit Field Type Reset Description

9 STIMENA9 R/W X

Bit mask to enable tracing on ITM stimulus port 9.

8 STIMENA8 R/W X

Bit mask to enable tracing on ITM stimulus port 8.

7 STIMENA7 R/W X

Bit mask to enable tracing on ITM stimulus port 7.

6 STIMENA6 R/W X

Bit mask to enable tracing on ITM stimulus port 6.

5 STIMENA5 R/W X

Bit mask to enable tracing on ITM stimulus port 5.

4 STIMENA4 R/W X

Bit mask to enable tracing on ITM stimulus port 4.

3 STIMENA3 R/W X

Bit mask to enable tracing on ITM stimulus port 3.

2 STIMENA2 R/W X

Bit mask to enable tracing on ITM stimulus port 2.

1 STIMENA1 R/W X

Bit mask to enable tracing on ITM stimulus port 1.

0 STIMENA0 R/W X

Bit mask to enable tracing on ITM stimulus port 0.

SWCU117A–February 2015–Revised March 2015

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