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10.2.1.19 AESCTL Register (Offset = 550h) [reset = X]
AESCTL is shown in Figure 10-21 and described in Table 10-29.
AES Input/Output Buffer Control
Figure 10-21. AESCTL Register
31 30 29 28 27 26 25 24
CONTEXT_RD SAVED_CONT SAVE_CONTE RESERVED CCM_M
Y EXT_RDY XT
R-1h R/W-X R/W-X R/W-X R/W-X
23 22 21 20 19 18 17 16
CCM_M CCM_L CCM RESERVED
R/W-X R/W-X R/W-X R/W-X
15 14 13 12 11 10 9 8
CBC_MAC RESERVED CTR_WIDTH
R/W-X R/W-X R/W-X
7 6 5 4 3 2 1 0
CTR_WIDTH CTR CBC KEY_SIZE DIR INPUT_RDY OUTPUT_RDY
R/W-X R/W-X R/W-X R-X R/W-X R/W-X R/W-X
Table 10-29. AESCTL Register Field Descriptions
Bit Field Type Reset Description
31 CONTEXT_RDY R 1h
If 1, this status bit indicates that the context data registers can be
overwritten and the Host is permitted to write the next context.
Writing a context means writing either a mode, the crypto length or
AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length
registers
30 SAVED_CONTEXT_RDY R/W X
If read as 1, this status bit indicates that an AES authentication TAG
and/or IV block(s) is/are available for the Host to retrieve. This bit is
only asserted if SAVE_CONTEXT is set to 1. The bit is mutually
exclusive with CONTEXT_RDY. Writing 1 clears the bit to zero,
indicating the Crypto peripheral can start its next operation. This bit
is also cleared when the 4th word of the output TAG and/or IV is
read. Note: All other mode bit writes will be ignored when this mode
bit is written with 1. Note: This bit is controlled automatically by the
Crypto peripheral for TAG read DMA operations. For typical use, this
bit does NOT need to be written, but is used for status reading only.
In this case, this status bit is automatically maintained by the Crypto
peripheral.
29 SAVE_CONTEXT R/W X
IV must be read before the AES engine can start a new operation.
28-25 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
24-22 CCM_M R/W X
Defines M that indicates the length of the authentication field for
CCM operations; the authentication field length equals two times the
value of CCM_M plus one. Note: The Crypto peripheral always
returns a 128-bit authentication field, of which the M least significant
bytes are valid. All values are supported.
21-19 CCM_L R/W X
Defines L that indicates the width of the length field for CCM
operations; the length field in bytes equals the value of CMM_L plus
one. All values are supported.
18 CCM R/W X
AES-CCM mode enable. AES-CCM is a combined mode, using AES
for both authentication and encryption. Note: Selecting AES-CCM
mode requires writing of AESDATALEN1.LEN_MSW and
AESDATALEN0.LEN_LSW after all other registers. Note: The CTR
mode bit in this register must also be set to 1 to enable AES-CTR;
selecting other AES modes than CTR mode is invalid.
17-16 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
844
SWCU117A–February 2015–Revised March 2015
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