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10.2.1.18 AESIV_0 to AESIV_3 Register (Offset = 540h to 54Ch) [reset = X]
AESIV_0 to AESIV_3 is shown in Figure 10-20 and described in Table 10-28.
AES Initialization Vector
Figure 10-20. AESIV_0 to AESIV_3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV
R/W-X
Table 10-28. AESIV_0 to AESIV_3 Register Field Descriptions
Bit Field Type Reset Description
31-0 IV R/W X
The interpretation of this field depends on the crypto operation
mode.
843
SWCU117A–February 2015–Revised March 2015
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