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Cryptography Registers

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10.2.1.17 AESKEY3_0 to AESKEY3_3 Register (Offset = 510h to 51Ch) [reset = X]

AESKEY3_0 to AESKEY3_3 is shown in Figure 10-19 and described in Table 10-27.

Clear AES_KEY3

Figure 10-19. AESKEY3_0 to AESKEY3_3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

KEY3

W-X

Table 10-27. AESKEY3_0 to AESKEY3_3 Register Field Descriptions

Bit Field Type Reset Description

31-0 KEY3 W X

AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x

= 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register

arrary. The interpretation of this field depends on the crypto

operation mode.

842

SWCU117A–February 2015–Revised March 2015

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