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10.2.1.9 DMABUSCFG Register (Offset = 78h) [reset = X]
DMABUSCFG is shown in Figure 10-11 and described in Table 10-19.
DMA Controller Master Configuration
Figure 10-11. DMABUSCFG Register
31 30 29 28 27 26 25 24
RESERVED
R/W-X
23 22 21 20 19 18 17 16
RESERVED
R/W-X
15 14 13 12 11 10 9 8
AHB_MST1_BURST_SIZE AHB_MST1_ID AHB_MST1_IN AHB_MST1_L AHB_MST1_BI
LE_EN CR_EN OCK_EN GEND
R/W-2h R/W-X R/W-1h R/W-X R/W-X
7 6 5 4 3 2 1 0
RESERVED
R/W-X
Table 10-19. DMABUSCFG Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
15-12 AHB_MST1_BURST_SIZ R/W 2h
Maximum burst size that can be performed on the AHB bus
E
2h = 4_BYTE : 4 bytes
3h = 8_BYTE : 8 bytes
4h = 16_BYTE : 16 bytes
5h = 32_BYTE : 32 bytes
6h = 64_BYTE : 64 bytes
11 AHB_MST1_IDLE_EN R/W X
Idle transfer insertion between consecutive burst transfers on AHB
0h = Do not insert idle transfers.
1h = Idle transfer insertion enabled
10 AHB_MST1_INCR_EN R/W 1h
Burst length type of AHB transfer
0h = Unspecified length burst transfers
1h = Fixed length bursts or single transfers
9 AHB_MST1_LOCK_EN R/W X
Locked transform on AHB
0h = Transfers are not locked
1h = Transfers are locked
8 AHB_MST1_BIGEND R/W X
Endianess for the AHB master
0h = Little Endian
1h = Big Endian
7-0 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
832
SWCU117A–February 2015–Revised March 2015
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