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10.2.1.7 DMACH1EXTADDR Register (Offset = 24h) [reset = X]
DMACH1EXTADDR is shown in Figure 10-9 and described in Table 10-17.
DMA Channel 1 External Address
Figure 10-9. DMACH1EXTADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
R/W-X
Table 10-17. DMACH1EXTADDR Register Field Descriptions
Bit Field Type Reset Description
31-0 ADDR R/W X
Channel external address value. Holds the last updated external
address after being sent to the master interface.
830
SWCU117A–February 2015–Revised March 2015
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