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10.2.1.6 DMACH1CTL Register (Offset = 20h) [reset = X]
DMACH1CTL is shown in Figure 10-8 and described in Table 10-16.
DMA Channel 1 Control
Figure 10-8. DMACH1CTL Register
31 30 29 28 27 26 25 24
RESERVED
R/W-X
23 22 21 20 19 18 17 16
RESERVED
R/W-X
15 14 13 12 11 10 9 8
RESERVED
R/W-X
7 6 5 4 3 2 1 0
RESERVED PRIO EN
R/W-X R/W-X R/W-X
Table 10-16. DMACH1CTL Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
1 PRIO R/W X
Channel priority: A channel with high priority will be served before a
channel with low priority in cases with simultaneous access
requests. If both channels have the same priority access of the
channels to the external port is arbitrated using a Round Robin
scheme.
0h = Priority low
1h = Priority high
0 EN R/W X
Channel enable: Note: Disabling an active channel will interrupt the
DMA operation. The ongoing block transfer will be completed, but no
new transfers will be requested.
0h = Channel disabled
1h = Channel enabled
829
SWCU117A–February 2015–Revised March 2015
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