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10.2.1.4 DMASTAT Register (Offset = 18h) [reset = X]
DMASTAT is shown in Figure 10-6 and described in Table 10-14 .
DMA Controller Status
Figure 10-6. DMASTAT Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED PORT_ERR RESERVED
R-X R-X R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED CH1_ACTIVE CH0_ACTIVE
R-X R-X R-X
Table 10-14. DMASTAT Register Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
17 PORT_ERR R X
Reflects possible transfer errors on the AHB port.
16-2 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
1 CH1_ACTIVE R X
This register field indicates if DMA channel 1 is active or not. 0: Not
active 1: Active
0 CH0_ACTIVE R X
This register field indicates if DMA channel 0 is active or not. 0: Not
active 1: Active
827
SWCU117A–February 2015–Revised March 2015
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