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Cryptography Registers
10.2.1 CRYPTO Registers
Table 10-10 lists the memory-mapped registers for the CRYPTO. All register offset addresses not listed in
Table 10-10 should be considered as reserved locations and the register contents should not be modified.
Table 10-10. CRYPTO Registers
Offset Acronym Register Name Section
0h DMACH0CTL DMA Channel 0 Control Section 10.2.1.1
4h DMACH0EXTADDR DMA Channel 0 External Address Section 10.2.1.2
Ch DMACH0LEN DMA Channel 0 Length Section 10.2.1.3
18h DMASTAT DMA Controller Status Section 10.2.1.4
1Ch DMASWRESET DMA Controller Software Reset Section 10.2.1.5
20h DMACH1CTL DMA Channel 1 Control Section 10.2.1.6
24h DMACH1EXTADDR DMA Channel 1 External Address Section 10.2.1.7
2Ch DMACH1LEN DMA Channel 1 Length Section 10.2.1.8
78h DMABUSCFG DMA Controller Master Configuration Section 10.2.1.9
7Ch DMAPORTERR DMA Controller Port Error Section 10.2.1.10
FCh DMAHWVER DMA Controller Version Section 10.2.1.11
400h KEYWRITEAREA Key Write Area Section 10.2.1.12
404h KEYWRITTENAREA Key Written Area Status Section 10.2.1.13
408h KEYSIZE Key Size Section 10.2.1.14
40Ch KEYREADAREA Key Read Area Section 10.2.1.15
500h to AESKEY2_0 to AESKEY2_3 Clear AES_KEY2/GHASH Key Section 10.2.1.16
50Ch
510h to AESKEY3_0 to AESKEY3_3 Clear AES_KEY3 Section 10.2.1.17
51Ch
540h to AESIV_0 to AESIV_3 AES Initialization Vector Section 10.2.1.18
54Ch
550h AESCTL AES Input/Output Buffer Control Section 10.2.1.19
554h AESDATALEN0 Crypto Data Length LSW Section 10.2.1.20
558h AESDATALEN1 Crypto Data Length MSW Section 10.2.1.21
55Ch AESAUTHLEN AES Authentication Length Section 10.2.1.22
560h AESDATAOUT0 Data Input/Output Section 10.2.1.23
560h AESDATAIN0 AES Data Input/Output 0 Section 10.2.1.24
564h AESDATAOUT1 AES Data Input/Output 3 Section 10.2.1.25
564h AESDATAIN1 AES Data Input/Output 1 Section 10.2.1.26
568h AESDATAOUT2 AES Data Input/Output 2 Section 10.2.1.27
568h AESDATAIN2 AES Data Input/Output 2 Section 10.2.1.28
56Ch AESDATAOUT3 AES Data Input/Output 3 Section 10.2.1.29
56Ch AESDATAIN3 Data Input/Output Section 10.2.1.30
570h to AESTAGOUT_0 to AESTAGOUT_3 AES Tag Output Section 10.2.1.31
57Ch
700h ALGSEL Master Algorithm Select Section 10.2.1.32
704h DMAPROTCTL Master Protection Control Section 10.2.1.33
740h SWRESET Software Reset Section 10.2.1.34
780h IRQTYPE Interrupt Configuration Section 10.2.1.35
784h IRQEN Interrupt Enable Section 10.2.1.36
788h IRQCLR Interrupt Clear Section 10.2.1.37
78Ch IRQSET Interrupt Set Section 10.2.1.38
790h IRQSTAT Interrupt Status Section 10.2.1.39
7FCh HWVER CTRL Module Version Section 10.2.1.40
823
SWCU117A–February 2015–Revised March 2015
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