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Factory Configuration (FCFG)

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9.2.1.77 PWD_CURR_95C Register (Offset = 3B0h) [reset = 4C627A3Bh]

PWD_CURR_95C is shown in Figure 9-98 and described in Table 9-100.

Power Down Current Control 95C

Figure 9-98. PWD_CURR_95C Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DELTA_CACHE_REF DELTA_RFMEM_RET

R-4Ch R-62h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DELTA_XOSC_LPM BASELINE

R-7Ah R-3Bh

Table 9-100. PWD_CURR_95C Register Field Descriptions

Bit Field Type Reset Description

31-24 DELTA_CACHE_REF R 4Ch

Additional maximum current, in units of 1uA, with cache retention

23-16 DELTA_RFMEM_RET R 62h

Additional maximum current, in 1uA units, with RF memory retention

15-8 DELTA_XOSC_LPM R 7Ah

Additional maximum current, in units of 1uA, with XOSC_HF on in

low-power mode

7-0 BASELINE R 3Bh

Worst-case baseline maximum powerdown current, in units of 0.5uA

794

Device Configuration SWCU117A–February 2015–Revised March 2015

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