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Factory Configuration (FCFG)

9.2.1.72 PWD_CURR_20C Register (Offset = 39Ch) [reset = 80BA608h]

PWD_CURR_20C is shown in Figure 9-93 and described in Table 9-95.

Power Down Current Control 20C

Figure 9-93. PWD_CURR_20C Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DELTA_CACHE_REF DELTA_RFMEM_RET

R-8h R-Bh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DELTA_XOSC_LPM BASELINE

R-A6h R-8h

Table 9-95. PWD_CURR_20C Register Field Descriptions

Bit Field Type Reset Description

31-24 DELTA_CACHE_REF R 8h

Additional maximum current, in units of 1uA, with cache retention

23-16 DELTA_RFMEM_RET R Bh

Additional maximum current, in 1uA units, with RF memory retention

15-8 DELTA_XOSC_LPM R A6h

Additional maximum current, in units of 1uA, with XOSC_HF on in

low-power mode

7-0 BASELINE R 8h

Worst-case baseline maximum powerdown current, in units of 0.5uA

789

SWCU117A–February 2015–Revised March 2015 Device Configuration

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