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9.2.1.69 OSC_CONF Register (Offset = 38Ch) [reset = X]
OSC_CONF is shown in Figure 9-90 and described in Table 9-92.
OSC Configuration
Figure 9-90. OSC_CONF Register
31 30 29 28 27 26 25 24
RESERVED ADC_SH_VBU ADC_SH_MOD ATESTLF_RC XOSCLF_REGULATOR_TRIM XOSCLF_CMIR
F_EN E_EN OSCLF_IBIAS_ RWR_RATIO
TRIM
R-3h R-1h R-1h R-X R-X R-X
23 22 21 20 19 18 17 16
XOSCLF_CMIRRWR_RATIO XOSC_HF_FAST_START XOSC_OPTIO RESERVED
N
R-X R-1h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED
R-0h
Table 9-92. OSC_CONF Register Field Descriptions
Bit Field Type Reset Description
31-30 RESERVED R 3h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
29 ADC_SH_VBUF_EN R 1h
Trim value for
DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN.
28 ADC_SH_MODE_EN R 1h
Trim value for
DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN.
27 ATESTLF_RCOSCLF_IBI R X
Trim value for
AS_TRIM
DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM.
26-25 XOSCLF_REGULATOR_ R X
Trim value for
TRIM
DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM.
24-21 XOSCLF_CMIRRWR_RA R X
Trim value for
TIO
DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO.
20-19 XOSC_HF_FAST_START R 1h
Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. This
trim value is not relevant for PG1 devices.
18 XOSC_OPTION R 0h
0: XOSC_HF unavailable (may not be bonded out) 1: XOSC_HF
available (default)
Reset differs depending on partnumber.
17-0 RESERVED R 0h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Reset holds trim value from production test.
786
Device Configuration SWCU117A–February 2015–Revised March 2015
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