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9.2.1.65 AMPCOMP_CTRL1 Register (Offset = 378h) [reset = FF183F47h]
AMPCOMP_CTRL1 is shown in Figure 9-86 and described in Table 9-88.
Amplitude Compensation Control
Figure 9-86. AMPCOMP_CTRL1 Register
31 30 29 28 27 26 25 24
RESERVED AMPCOMP_RE RESERVED
Q_MODE
R-1h R-1h R-3Fh
23 22 21 20 19 18 17 16
IBIAS_OFFSET IBIAS_INIT
R-1h R-8h
15 14 13 12 11 10 9 8
LPM_IBIAS_WAIT_CNT_FINAL
R-3Fh
7 6 5 4 3 2 1 0
CAP_STEP IBIASCAP_HPTOLP_OL_CNT
R-4h R-7h
Table 9-88. AMPCOMP_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
31 RESERVED R 1h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
30 AMPCOMP_REQ_MODE R 1h
Trim value for
DDI_0_OSC:AMPCOMPCTL.AMPCOMP_REQ_MODE.
29-24 RESERVED R 3Fh
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
23-20 IBIAS_OFFSET R 1h
Offset values of XOSC IBIAS trim. IBIAS trim value would always be
greater than or equal to this offset in both HPM and LPM.
19-16 IBIAS_INIT R 8h
Initial value of XOSC IBIAS trim. During ramping up, IBIAS is set to
IBIAS_OFFSET + IBIAS_INIT.
15-8 LPM_IBIAS_WAIT_CNT_ R 3Fh
FSM waits for ddi_lpm_ibias_wait_cnt_final clock cycles in
FINAL
IDAC_DECREMENT_WITH_MEASURE states in order to
compensate slow response of the xtal. 8-bits.
7-4 CAP_STEP R 4h
Step size of XOSC CAP trim (both Q1 and Q2) during XOSC mode
transition. Can vary from 6 to 12. Other values are possible but not
valid.
3-0 IBIASCAP_HPTOLP_OL_ R 7h
During HPM to LPM transition, CAP trim and IBIAS trim should be
CNT
modified by this amount. IBIAS and CAP trim open loop count.
CAP_REM is remainder of the CAP that is left to reach the final cap
value. Do not need to program this. CAP_TRIM = CAP_INIT -
CAP_STEP*IBIASCAP_HPTOLP_OL_CNT - CAP_REM;
IBIAS_TRIM = IBIAS_INIT - 1*IBIASCAP_HPTOLP_OL_CNT; Here,
cap_init is decimal conversion of cap_init_col and cap_init_row.
782
Device Configuration SWCU117A–February 2015–Revised March 2015
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