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9.2.1.62 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register (Offset = 36Ch) [reset = 300080h]
SOC_ADC_REF_TRIM_AND_OFFSET_EXT is shown in Figure 9-83 and described in Table 9-85.
AUX_ADC Reference Trim and Offset for External Reference Mode
Figure 9-83. SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
SOC_ADC_EXT_OFFSET_TEMP1
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-C002h
7 6 5 4 3 2 1 0
RESERVED SOC_ADC_REF_VOLTAGE_TRIM_TEMP1
R-C002h R-0h
Table 9-85. SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Reset holds trim value from production test.
23-16 SOC_ADC_EXT_OFFSET R 0h
SOC_ADC offset in external reference mode at temperature 1 (30C).
_TEMP1
Signed 8-bit number. Calculated in production test..
Reset holds trim value from production test.
15-6 RESERVED R C002h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
5-0 SOC_ADC_REF_VOLTA R 0h
Value to write in ADI_4_AUX:ADCREF1.VTRIM at temperature 1
GE_TRIM_TEMP1
(30C).
Reset holds trim value from production test.
779
SWCU117A–February 2015–Revised March 2015 Device Configuration
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