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Factory Configuration (FCFG)

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9.2.1.61 SOC_ADC_OFFSET_INT Register (Offset = 368h) [reset = 0h]

SOC_ADC_OFFSET_INT is shown in Figure 9-82 and described in Table 9-84.

AUX_ADC Temperature Offsets in Absolute Reference Mode

Figure 9-82. SOC_ADC_OFFSET_INT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SOC_ADC_REL_OFFSET_TEMP2 SOC_ADC_REL_OFFSET_TEMP1

R-0h R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SOC_ADC_ABS_OFFSET_TEMP2 SOC_ADC_ABS_OFFSET_TEMP1

R-0h R-0h

Table 9-84. SOC_ADC_OFFSET_INT Register Field Descriptions

Bit Field Type Reset Description

31-24 SOC_ADC_REL_OFFSET R 0h

SOC_ADC offset in relative reference mode at temperature 2 (85C).

_TEMP2

Signed 8-bit number. Calculated in production test..

Reset holds trim value from production test.

23-16 SOC_ADC_REL_OFFSET R 0h

SOC_ADC offset in relative reference mode at temperature 1 (30C).

_TEMP1

Signed 8-bit number. Calculated in production test..

Reset holds trim value from production test.

15-8 SOC_ADC_ABS_OFFSE R 0h

SOC_ADC offset in absolute reference mode at temperature 2

T_TEMP2

(85C). Signed 8-bit number. Calculated in production test..

Reset holds trim value from production test.

7-0 SOC_ADC_ABS_OFFSE R 0h

SOC_ADC offset in absolute reference mode at temperature 1

T_TEMP1

(30C). Signed 8-bit number. Calculated in production test..

Reset holds trim value from production test.

778

Device Configuration SWCU117A–February 2015–Revised March 2015

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