User manual

Factory Configuration (FCFG)

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9.2.1.59 SOC_ADC_REL_GAIN Register (Offset = 360h) [reset = 0h]

SOC_ADC_REL_GAIN is shown in Figure 9-80 and described in Table 9-82.

AUX_ADC Gain in Relative Reference Mode

Figure 9-80. SOC_ADC_REL_GAIN Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SOC_ADC_REL_GAIN_TEMP2

R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SOC_ADC_REL_GAIN_TEMP1

R-0h

Table 9-82. SOC_ADC_REL_GAIN Register Field Descriptions

Bit Field Type Reset Description

31-16 SOC_ADC_REL_GAIN_T R 0h

SOC_ADC gain in relative reference mode at temperature 2 (85C).

EMP2

Calculated in production test..

Reset holds trim value from production test.

15-0 SOC_ADC_REL_GAIN_T R 0h

SOC_ADC gain in relative reference mode at temperature 1 (30C).

EMP1

Calculated in production test..

Reset holds trim value from production test.

776

Device Configuration SWCU117A–February 2015–Revised March 2015

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