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Factory Configuration (FCFG)

9.2.1.58 SOC_ADC_ABS_GAIN Register (Offset = 35Ch) [reset = 0h]

SOC_ADC_ABS_GAIN is shown in Figure 9-79 and described in Table 9-81.

AUX_ADC Gain in Absolute Reference Mode

Figure 9-79. SOC_ADC_ABS_GAIN Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SOC_ADC_ABS_GAIN_TEMP2

R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SOC_ADC_ABS_GAIN_TEMP1

R-0h

Table 9-81. SOC_ADC_ABS_GAIN Register Field Descriptions

Bit Field Type Reset Description

31-16 SOC_ADC_ABS_GAIN_T R 0h

SOC_ADC gain in absolute reference mode at temperature 2 (85C).

EMP2

Calculated in production test.

Reset holds log information from production test.

15-0 SOC_ADC_ABS_GAIN_T R 0h

SOC_ADC gain in absolute reference mode at temperature 1 (30C).

EMP1

Calculated in production test..

Reset holds log information from production test.

775

SWCU117A–February 2015–Revised March 2015 Device Configuration

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