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Factory Configuration (FCFG)
9.2.1.52 MISC_OTP_DATA Register (Offset = 320h) [reset = X]
MISC_OTP_DATA is shown in Figure 9-73 and described in Table 9-75.
Misc OTP Data
Figure 9-73. MISC_OTP_DATA Register
31 30 29 28 27 26 25 24
RCOSC_HF_ITUNE RCOSC_HF_CRIM
R-X R-X
23 22 21 20 19 18 17 16
RCOSC_HF_CRIM PER_M
R-X R-1h
15 14 13 12 11 10 9 8
PER_M PER_E PO_TAIL_RES_TRIM
R-1h R-4h R-6h
7 6 5 4 3 2 1 0
TEST_PROGRAM_REV
R-0h
Table 9-75. MISC_OTP_DATA Register Field Descriptions
Bit Field Type Reset Description
31-28 RCOSC_HF_ITUNE R X
Trim value that migth become into use for cc26xx PG2.2 and cc13xx
PG2.0. Trim value for
DDI_0_OSC:RCOSCHFCTL.RCOSCHF_ITUNE_TRIM.
27-20 RCOSC_HF_CRIM R X
Trim value that migth become into use for cc26xx PG2.2 and cc13xx
PG2.0. Trim value for
DDI_0_OSC:RCOSCHFCTL.RCOSCHF_CTRIM.
19-15 PER_M R 1h
Trim value for AON_WUC:OSCCFG.PER_M.
14-12 PER_E R 4h
Trim value for AON_WUC:OSCCFG.PER_E.
11-8 PO_TAIL_RES_TRIM R 6h
Trim value for DLO_DTX:PLLCTL1.PO_TAIL_RES_TRIM.
7-0 TEST_PROGRAM_REV R 0h
The revision of the test program used in the production process
when FCFG1 was programmed.
Reset holds log information from production test.
769
SWCU117A–February 2015–Revised March 2015 Device Configuration
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