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Factory Configuration (FCFG)

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9.2.1.47 MISC_TRIM Register (Offset = 30Ch) [reset = FFFFFF33h]

MISC_TRIM is shown in Figure 9-68 and described in Table 9-70.

Miscellaneous Trim Parameters

Figure 9-68. MISC_TRIM Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

R-FFFFFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED TEMPVSLOPE

R-FFFFFFh R-33h

Table 9-70. MISC_TRIM Register Field Descriptions

Bit Field Type Reset Description

31-8 RESERVED R FFFFFFh

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

7-0 TEMPVSLOPE R 33h

Signed byte value representing the TEMP slope with battery voltage,

in degrees C / V, with four fractional bits.

764

Device Configuration SWCU117A–February 2015–Revised March 2015

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