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9.2.1.40 ANA2_TRIM Register (Offset = 2B4h) [reset = X]
ANA2_TRIM is shown in Figure 9-61 and described in Table 9-63.
Misc Analog Trim
Figure 9-61. ANA2_TRIM Register
31 30 29 28 27 26 25 24
RCOSCHFCTR RCOSCHFCTRIMFRACT RESERVED SET_RCOSC_
IMFRACT_EN HF_FINE_RESI
STOR
R-1h R-0h R-1h R-X
23 22 21 20 19 18 17 16
SET_RCOSC_ ATESTLF_UDI NANOAMP_RES_TRIM
HF_FINE_RESI GLDO_IBIAS_T
STOR RIM
R-X R-1h R-0h
15 14 13 12 11 10 9 8
RESERVED DITHER_EN DCDC_IPEAK
R-Fh R-X R-4h
7 6 5 4 3 2 1 0
DEAD_TIME_TRIM DCDC_LOW_EN_SEL DCDC_HIGH_EN_SEL
R-1h R-7h R-7h
Table 9-63. ANA2_TRIM Register Field Descriptions
Bit Field Type Reset Description
31 RCOSCHFCTRIMFRACT R 1h
Value will be written to
_EN
DDI_0_OSC:CTL1.RCOSCHFCTRIMFRACT_EN by boot FW while
in safezone.
30-26 RCOSCHFCTRIMFRACT R 0h
Value will be written to DDI_0_OSC:CTL1.RCOSCHFCTRIMFRACT
by boot FW while in safezone.
Reset holds trim value from production test.
25 RESERVED R 1h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
24-23 SET_RCOSC_HF_FINE_ R X
Value will be written to
RESISTOR
DDI_0_OSC:ATESTCTL.SET_RCOSC_HF_FINE_RESISTOR by
boot FW while in safezone.
22 ATESTLF_UDIGLDO_IBI R 1h
Value will be written
AS_TRIM
DDI_0_OSC:ATESTCTL.ATESTLF_UDIGLDO_IBIAS_TRIM by boot
FW while in safezone.
21-16 NANOAMP_RES_TRIM R 0h
Value will be written to
DDI_0_OSC:ADCDOUBLERNANOAMPCTL.NANOAMP_RES_TRIM
by boot FW while in safezone.
Reset holds trim value from production test.
15-12 RESERVED R Fh
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
11 DITHER_EN R X
Value will be written to ADI_3_REFSYS:DCDCCTL5.DITHER_EN by
boot FW while in safezone.
10-8 DCDC_IPEAK R 4h
Value will be written to ADI_3_REFSYS:DCDCCTL5.IPEAK by boot
FW while in safezone.
7-6 DEAD_TIME_TRIM R 1h
Value will be written to
ADI_3_REFSYS:DCDCCTL4.DEADTIME_TRIM by boot FW while in
safezone.
5-3 DCDC_LOW_EN_SEL R 7h
Value will be written to ADI_3_REFSYS:DCDCCTL4.LOW_EN_SEL
by boot FW while in safezone.
755
SWCU117A–February 2015–Revised March 2015 Device Configuration
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