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9.2.1.39 FLASH_OTP_DATA3 Register (Offset = 2B0h) [reset = X]
FLASH_OTP_DATA3 is shown in Figure 9-60 and described in Table 9-62.
Flash OTP Data 3
Figure 9-60. FLASH_OTP_DATA3 Register
31 30 29 28 27 26 25 24
EC_STEP_SIZE
R-X
23 22 21 20 19 18 17 16
EC_STEP_SIZ DO_PRECOND MAX_EC_LEVEL TRIM_1P7
E
R-X R-X R-4h R-1h
15 14 13 12 11 10 9 8
FLASH_SIZE
R-0h
7 6 5 4 3 2 1 0
WAIT_SYSCODE
R-3h
Table 9-62. FLASH_OTP_DATA3 Register Field Descriptions
Bit Field Type Reset Description
31-23 EC_STEP_SIZE R X
Value will be written to FLASH:FSM_STEP_SIZE.EC_STEP_SIZE
by the flash device driver when a erase/program operation is
initiated.
22 DO_PRECOND R X
Value will be written to FLASH:FSM_ST_MACHINE.DO_PRECOND
by the flash device driver when a erase/program operation is
initiated. Note that during a Total Erase operation the flash bank will
always be erased with Precondition enabled independent of the
value of this FCFG1 bit field.
21-18 MAX_EC_LEVEL R 4h
Value will be written to FLASH:FSM_ERA_PUL.MAX_EC_LEVEL by
the flash device driver when a erase/program operation is initiated.
17-16 TRIM_1P7 R 1h
Value will be written to FLASH:FSEQPMP.TRIM_1P7 by the flash
device driver when a erase/program operation is initiated.
15-8 FLASH_SIZE R 0h
Value will be written to FLASH:FLASH_SIZE.SECTORS by the boot
FW while in safe zone. This register will be write protected by the
boot FW by setting FLASH:CFG.CONFIGURED.
Reset differs depending on partnumber.
7-0 WAIT_SYSCODE R 3h
Value will be written to FLASH:WAIT_SYSCODE.WAIT_SYSCODE
by boot FW code while in safezone.
754
Device Configuration SWCU117A–February 2015–Revised March 2015
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