User manual

www.ti.com

Factory Configuration (FCFG)

9.2.1.34 FLASH_ERA_PW Register (Offset = 18Ch) [reset = FA0h]

FLASH_ERA_PW is shown in Figure 9-55 and described in Table 9-57.

Flash Erase Pulse Width

Figure 9-55. FLASH_ERA_PW Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ERASE_PW

R-FA0h

Table 9-57. FLASH_ERA_PW Register Field Descriptions

Bit Field Type Reset Description

31-0 ERASE_PW R FA0h

Erase pulse width in half-microseconds. Value will be converted to

number of FCLK cycles by the flash device driver and the converted

value is written to FLASH:FSM_ERA_PW.FSM_ERA_PW when a

erase/program operation is initiated.

749

SWCU117A–February 2015–Revised March 2015 Device Configuration

Submit Documentation Feedback