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9.2.1.24 SHDW_ANA_TRIM Register (Offset = 13Ch) [reset = 0h]
SHDW_ANA_TRIM is shown in Figure 9-45 and described in Table 9-47.
Shadow of EFUSE:ANA_TRIM
Figure 9-45. SHDW_ANA_TRIM Register
31 30 29 28 27 26 25 24
RESERVED BOD_BANDGAP_TRIM_CNF VDDR_ENABL
E_PG1
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
VDDR_OK_HY IPTAT_TRIM VDDR_TRIM
S
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
TRIMBOD_INTMODE TRIMBOD_EXTMODE
R-0h R-0h
7 6 5 4 3 2 1 0
TRIMBOD_EXTMODE TRIMTEMP
R-0h R-0h
Table 9-47. SHDW_ANA_TRIM Register Field Descriptions
Bit Field Type Reset Description
31-27 RESERVED R 0h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Reset depends on eFuse value.
26-25 BOD_BANDGAP_TRIM_ R 0h
Shadow of EFUSE:ANA_TRIM.BOD_BANDGAP_TRIM_CNF, ie in
CNF
efuse row number 12
Reset depends on eFuse value.
24 VDDR_ENABLE_PG1 R 0h
Shadow of EFUSE:ANA_TRIM.VDDR_ENABLE_PG1, ie in efuse
row number 12
Reset depends on eFuse value.
23 VDDR_OK_HYS R 0h
Shadow of EFUSE:ANA_TRIM.VDDR_OK_HYS, ie in efuse row
number 12
Reset depends on eFuse value.
22-21 IPTAT_TRIM R 0h
Shadow of EFUSE:ANA_TRIM.IPTAT_TRIM, ie in efuse row number
12
Reset depends on eFuse value.
20-16 VDDR_TRIM R 0h
Shadow of EFUSE:ANA_TRIM.VDDR_TRIM, ie in efuse row number
12
Reset depends on eFuse value.
15-11 TRIMBOD_INTMODE R 0h
Shadow of EFUSE:ANA_TRIM.TRIMBOD_INTMODE, ie in efuse
row number 12
Reset depends on eFuse value.
10-6 TRIMBOD_EXTMODE R 0h
Shadow of EFUSE:ANA_TRIM.TRIMBOD_EXTMODE, ie in efuse
row number 12
Reset depends on eFuse value.
5-0 TRIMTEMP R 0h
Shadow of EFUSE:ANA_TRIM.TRIMTEMP, ie in efuse row number
12
Reset depends on eFuse value.
739
SWCU117A–February 2015–Revised March 2015 Device Configuration
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