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9.2.1.23 SHDW_OSC_BIAS_LDO_TRIM Register (Offset = 138h) [reset = 0h]
SHDW_OSC_BIAS_LDO_TRIM is shown in Figure 9-44 and described in Table 9-46.
Shadow of EFUSE:OSC_BIAS_LDO_TRIM
Figure 9-44. SHDW_OSC_BIAS_LDO_TRIM Register
31 30 29 28 27 26 25 24
RESERVED SET_RCOSC_HF_COARSE_RE TRIMMAG
SISTOR
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
TRIMMAG TRIMIREF ITRIM_DIG_LDO
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
VTRIM_DIG VTRIM_COARSE
R-0h R-0h
7 6 5 4 3 2 1 0
RCOSCHF_CTRIM
R-0h
Table 9-46. SHDW_OSC_BIAS_LDO_TRIM Register Field Descriptions
Bit Field Type Reset Description
31-29 RESERVED R 0h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Reset depends on eFuse value.
28-27 SET_RCOSC_HF_COAR R 0h
Shadow of
SE_RESISTOR
EFUSE:OSC_BIAS_LDO_TRIM.SET_RCOSC_HF_COARSE_RESI
STOR, ie in efuse row number 11
Reset depends on eFuse value.
26-23 TRIMMAG R 0h
Shadow of EFUSE:OSC_BIAS_LDO_TRIM.TRIMMAG, ie in efuse
row number 11
Reset depends on eFuse value.
22-18 TRIMIREF R 0h
Shadow of EFUSE:OSC_BIAS_LDO_TRIM.TRIMIREF, ie in efuse
row number 11
Reset depends on eFuse value.
17-16 ITRIM_DIG_LDO R 0h
Shadow of EFUSE:OSC_BIAS_LDO_TRIM.ITRIM_DIG_LDO, ie in
efuse row number 11
Reset depends on eFuse value.
15-12 VTRIM_DIG R 0h
Shadow of EFUSE:OSC_BIAS_LDO_TRIM.VTRIM_DIG, ie in efuse
row number 11
Reset depends on eFuse value.
11-8 VTRIM_COARSE R 0h
Shadow of EFUSE:OSC_BIAS_LDO_TRIM.VTRIM_COARSE, ie in
efuse row number 11
Reset depends on eFuse value.
7-0 RCOSCHF_CTRIM R 0h
Shadow of EFUSE:OSC_BIAS_LDO_TRIM.RCOSCHF_CTRIM, ie in
efuse row number 11
Reset depends on eFuse value.
738
Device Configuration SWCU117A–February 2015–Revised March 2015
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