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Factory Configuration (FCFG)

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9.2.1.9 CONFIG_SYNTH_DIV10 Register (Offset = E4h) [reset = FFFFFFFFh]

CONFIG_SYNTH_DIV10 is shown in Figure 9-30 and described in Table 9-32.

Configuration of Synthesizer in Divide-by-10 Mode Divide-by-10 mode is only available for CC13xx.

Figure 9-30. CONFIG_SYNTH_DIV10 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED RFC_MDM_DEMIQMC0

R-Fh R-FFFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RFC_MDM_DEMIQMC0 LDOVCO_TRIM_OUTPUT SLDO_TRIM_OUTPUT

R-FFFFh R-3Fh R-3Fh

Table 9-32. CONFIG_SYNTH_DIV10 Register Field Descriptions

Bit Field Type Reset Description

31-28 RESERVED R Fh

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

27-12 RFC_MDM_DEMIQMC0 R FFFFh

Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and

RFC_MDM:DEMIQMC0.PHASEFACTOR Value is read by RF Core

ROM FW during RF Core initialization.

11-6 LDOVCO_TRIM_OUTPU R 3Fh

Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT. Value is

read by RF Core ROM FW during RF Core initialization.

5-0 SLDO_TRIM_OUTPUT R 3Fh

Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read

by RF Core ROM FW during RF Core initialization.

724

Device Configuration SWCU117A–February 2015–Revised March 2015

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