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9.1.1.21 CCFG_PROT_127_96 Register (Offset = FFCh) [reset = FFFFFFFFh]
CCFG_PROT_127_96 is shown in Figure 9-21 and described in Table 9-22.
Protect Sectors 96-127 Each bit write protects one sector from being both programmed and erased. Bit
must be set to 0 in order to enable sector write protect. Not in use on CC26xx.
Figure 9-21. CCFG_PROT_127_96 Register
31 30 29 28 27 26 25 24
WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S
EC_127 EC_126 EC_125 EC_124 EC_123 EC_122 EC_121 EC_120
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h
23 22 21 20 19 18 17 16
WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S
EC_119 EC_118 EC_117 EC_116 EC_115 EC_114 EC_113 EC_112
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h
15 14 13 12 11 10 9 8
WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S
EC_111 EC_110 EC_109 EC_108 EC_107 EC_106 EC_105 EC_104
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h
7 6 5 4 3 2 1 0
WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S WRT_PROT_S
EC_103 EC_102 EC_101 EC_100 EC_99 EC_98 EC_97 EC_96
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h
Table 9-22. CCFG_PROT_127_96 Register Field Descriptions
Bit Field Type Reset Description
31 WRT_PROT_SEC_127 R/W 1h
0: Sector protected
30 WRT_PROT_SEC_126 R/W 1h
0: Sector protected
29 WRT_PROT_SEC_125 R/W 1h
0: Sector protected
28 WRT_PROT_SEC_124 R/W 1h
0: Sector protected
27 WRT_PROT_SEC_123 R/W 1h
0: Sector protected
26 WRT_PROT_SEC_122 R/W 1h
0: Sector protected
25 WRT_PROT_SEC_121 R/W 1h
0: Sector protected
24 WRT_PROT_SEC_120 R/W 1h
0: Sector protected
23 WRT_PROT_SEC_119 R/W 1h
0: Sector protected
22 WRT_PROT_SEC_118 R/W 1h
0: Sector protected
21 WRT_PROT_SEC_117 R/W 1h
0: Sector protected
20 WRT_PROT_SEC_116 R/W 1h
0: Sector protected
19 WRT_PROT_SEC_115 R/W 1h
0: Sector protected
18 WRT_PROT_SEC_114 R/W 1h
0: Sector protected
17 WRT_PROT_SEC_113 R/W 1h
0: Sector protected
16 WRT_PROT_SEC_112 R/W 1h
0: Sector protected
15 WRT_PROT_SEC_111 R/W 1h
0: Sector protected
14 WRT_PROT_SEC_110 R/W 1h
0: Sector protected
13 WRT_PROT_SEC_109 R/W 1h
0: Sector protected
12 WRT_PROT_SEC_108 R/W 1h
0: Sector protected
11 WRT_PROT_SEC_107 R/W 1h
0: Sector protected
10 WRT_PROT_SEC_106 R/W 1h
0: Sector protected
712
Device Configuration SWCU117A–February 2015–Revised March 2015
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