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VIMS Registers

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7.7.2.91 FSM_ERA_PUL Register (Offset = 226Ch) [reset = X]

FSM_ERA_PUL is shown in Figure 7-101 and described in Table 7-98.

Internal. Only to be used through TI provided API.

Figure 7-101. FSM_ERA_PUL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED MAX_EC_LEVEL

R-X R/W-4h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED MAX_ERA_PUL

R-X R/W-BB8h

Table 7-98. FSM_ERA_PUL Register Field Descriptions

Bit Field Type Reset Description

31-20 RESERVED R X

Internal. Only to be used through TI provided API.

19-16 MAX_EC_LEVEL R/W 4h

Internal. Only to be used through TI provided API.

15-12 RESERVED R X

Internal. Only to be used through TI provided API.

11-0 MAX_ERA_PUL R/W BB8h

Internal. Only to be used through TI provided API.

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Versatile Instruction Memory System (VIMS) SWCU117A–February 2015–Revised March 2015

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