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VIMS Registers

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7.7.2.73 FSM_PE_OSU Register (Offset = 2210h) [reset = X]

FSM_PE_OSU is shown in Figure 7-83 and described in Table 7-80.

Internal. Only to be used through TI provided API.

Figure 7-83. FSM_PE_OSU Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PGM_OSU ERA_OSU

R-X R/W-X R/W-X

Table 7-80. FSM_PE_OSU Register Field Descriptions

Bit Field Type Reset Description

31-16 RESERVED R X

Internal. Only to be used through TI provided API.

15-8 PGM_OSU R/W X

Internal. Only to be used through TI provided API.

7-0 ERA_OSU R/W X

Internal. Only to be used through TI provided API.

618

Versatile Instruction Memory System (VIMS) SWCU117A–February 2015–Revised March 2015

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