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Cortex-M3 Processor Registers

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2.7.1.9 STIM8 Register (Offset = 20h) [reset = 0h]

STIM8 is shown in Figure 2-12 and described in Table 2-35.

Stimulus Port 8

Figure 2-12. STIM8 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

STIM8

R/W-0h

Table 2-35. STIM8 Register Field Descriptions

Bit Field Type Reset Description

31-0 STIM8 R/W 0h

A write to this location causes data to be written into the FIFO if

TER.STIMENA8 is set. Reading from the stimulus port returns the

FIFO status in bit [0]: 0 = full, 1 = not full. The polled FIFO interface

does not provide an atomic read-modify-write, so it's users

responsibility to ensure exclusive read-modify-write if this ITM port is

used concurrently by interrupts or other threads.

SWCU117A–February 2015–Revised March 2015

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