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VIMS Registers

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7.7.2.49 FEFUSECTL Register (Offset = 209Ch) [reset = X]

FEFUSECTL is shown in Figure 7-59 and described in Table 7-56.

Internal. Only to be used through TI provided API.

Figure 7-59. FEFUSECTL Register

31 30 29 28 27 26 25 24

RESERVED CHAIN_SEL

R-X R/W-7h

23 22 21 20 19 18 17 16

RESERVED WRITE_EN BP_SEL

R-X R/W-X R/W-1h

15 14 13 12 11 10 9 8

RESERVED EF_CLRZ

R-X R/W-1h

7 6 5 4 3 2 1 0

RESERVED EF_TEST EFUSE_EN

R-X R/W-X R/W-Ah

Table 7-56. FEFUSECTL Register Field Descriptions

Bit Field Type Reset Description

31-27 RESERVED R X

Internal. Only to be used through TI provided API.

26-24 CHAIN_SEL R/W 7h

Internal. Only to be used through TI provided API.

23-18 RESERVED R X

Internal. Only to be used through TI provided API.

17 WRITE_EN R/W X

Internal. Only to be used through TI provided API.

16 BP_SEL R/W 1h

Internal. Only to be used through TI provided API.

15-9 RESERVED R X

Internal. Only to be used through TI provided API.

8 EF_CLRZ R/W 1h

Internal. Only to be used through TI provided API.

7-5 RESERVED R X

Internal. Only to be used through TI provided API.

4 EF_TEST R/W X

Internal. Only to be used through TI provided API.

3-0 EFUSE_EN R/W Ah

Internal. Only to be used through TI provided API.

594

Versatile Instruction Memory System (VIMS) SWCU117A–February 2015–Revised March 2015

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