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7.7.2.1 STAT Register (Offset = 1Ch) [reset = X]
STAT is shown in Figure 7-11 and described in Table 7-8.
FMC and Efuse Status
Figure 7-11. STAT Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
EFUSE_BLAN EFUSE_TIMEO EFUSE_CRC_ EFUSE_ERRCODE
K UT ERROR
R-X R-X R-X R-X
7 6 5 4 3 2 1 0
RESERVED SAMHOLD_DI BUSY POWER_MOD
S E
R-X R-X R-X R-X
Table 7-8. STAT Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
15 EFUSE_BLANK R X
Efuse scanning detected if fuse ROM is blank: 0 : Not blank 1 :
Blank
14 EFUSE_TIMEOUT R X
Efuse scanning resulted in timeout error. 0 : No Timeout error 1 :
Timeout Error
13 EFUSE_CRC_ERROR R X
Efuse scanning resulted in scan chain CRC error. 0 : No CRC error
1 : CRC Error
12-8 EFUSE_ERRCODE R X
Same as EFUSEERROR.CODE
7-3 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
2 SAMHOLD_DIS R X
Status indicator of flash sample and hold sequencing logic. This bit
will go to 1 some delay after CFG.DIS_IDLE is set to 1. 0: Not
disabled 1: Sample and hold disabled and stable
1 BUSY R X
Fast version of the FMC FMSTAT.BUSY bit. This flag is valid
immediately after the operation setting it (FMSTAT.BUSY is delayed
some cycles) 0 : Not busy 1 : Busy
0 POWER_MODE R X
Power state of the flash sub-system. 0 : Active 1 : Low power
546
Versatile Instruction Memory System (VIMS) SWCU117A–February 2015–Revised March 2015
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